1. Field of the Invention
The present invention relates to a manufacturing method of an integrated chip, and more particularly, to a manufacturing method of an integrated chip including devices with different functions.
2. Description of the Prior Art
According to the current semiconductor industry, a single production line, usually a standard foundry, is used to fabricate integrated circuits into chips, and then a semiconductor wafer including the integrated chips is outsourced to other manufactures respectively specialized in the operations of test and packaging. Generally speaking, the integrated chip, such as a microprocessor unit or an application specific integrated circuit (ASIC), includes a variety of devices, such as logic circuits, volatile memories, non-volatile memories, mixed-mode circuits, etc., interconnected by peripheral circuits to form a complete circuit for a specific function. Each of the above-mentioned devices has different structural characteristics and requires different processes for fabrication. Consequently, the prior art method of fabricating the devices by a single production line suffers many problems.
Taking an embedded memory for an example, an embedded memory includes memory cell arrays and high-speed logic circuit devices integrated and formed onto a single chip for significantly reducing the circuit area and raising the signal processing speed. FIG. 1 is a structural diagram of an embedded memory 10. As shown in FIG. 1, the embedded memory 10 comprises a memory array area 12 and a peripheral circuit region 14 defined on a surface of a silicon substrate 16 of a semiconductor wafer (not shown in FIG. 1). The memory array area 12 comprises a cell well 18, and a plurality of gates 20 are formed on the cell well 18 for constructing a MOS transistor. The periphery circuit region 14 comprises at least an N-well 22 and a P-well 24, and a plurality of gates 20 are formed on the N-well 22 and the P-well 24 for respectively constructing a PMOS transistor and an NMOS transistor. A spacer 28 is formed around each gate 20, 26, and an LDD 30, a source 32 and a drain 34 are formed on either side of each gate 20, 26 on the surface of the silicon substrate 16.
According to the embedded memory 10, the memory cell arrays in the memory array area 12 and the logic circuit devices in the peripheral circuit region 14 respectively have specific functions. Therefore, the prior art method of manufacturing the embedded memory 10 cannot conform to the requirements of both the memory cell array and logic circuit device. For example, the logic circuit devices in the periphery circuit region 14 need to have low resistance and high speed, and a self-alignment silicide (salicide) process is performed to form a silicide layer on the gate 26, source 32 and drain 34 of the MOS transistor for reducing interface resistance. However, a self-aligned-contact (SAC) processdeveloped for solving the electrical connection problem of memory cells formed in the memory array area 12 involves forming a cap layer composed of silicon nitride on a top surface of the gate 20 of the MOS transistor and used as an isolation mask in the subsequent SAC process. The problem is the inability to simultaneously perform both of the above processes, so that the prior art method of manufacturing the embedded memory 10 provides two ways for solving this problem. One is based on the salicide process of the peripheral circuit region 14 and therefore forms a silicide layer. The other is based on the SAC process of the memory array area 12 and therefore does not form a silicide layer. However, the former way increases junction leakage current and further adversely affects storage charge refresh times, and the latter way increases surface resistance of the gate 26, source 32 and drain 24 of the MOS transistor in the periphery circuit region 14, which results in decreasing access speed.
Additionally, the depth of the gate 26 of the PMOS transistor in the peripheral circuit region 14 generally is kept at 2000˜3000 Å for preventing boron penetration issues. For combining the fabrication of the gates 20, 26 in the peripheral circuit region 14 and in the memory array area 12, according to the prior art method of manufacturing the embedded memory 10, the depth of the gate 20 in the memory array area 12 will increase to fit in with the depth of the gate 26 in the periphery circuit region 14. As the integration of the memory array area 12 increases, the aspect ratio between gates 20 greatly increases. Thus, over-hanging easily occurs between two neighboring gates in the memory array area 12 when filling an inter-layer dielectric (ILD) layer. A void bridge may then be formed, creating an electrical connection with a contact plug formed between two neighboring gates, and leading to short-circuiting.
The prior art method of manufacturing the embedded memory 10 by a single production line suffers the problem of defective products due to the difficulties in combining the processes of the logic circuit devices and the memory cell arrays. Additionally, either hardware (such as equipment) or software (such as training of staff) of the standard foundry is not established for fabricating memory cells, therefore, the standard foundry must experience a manufacturing learning curve when fabricating the embedded memory, resulting in a reduced yield and output.